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Texas Instruments /MSP432P401M /FLCTL /FLCTL_PRGBRST_CTLSTAT

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Interpret as FLCTL_PRGBRST_CTLSTAT

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (START)START 0 (TYPE_0)TYPE 0 (LEN_0)LEN0 (AUTO_PRE_0)AUTO_PRE 0 (AUTO_PST_0)AUTO_PST 0 (BURST_STATUS_0)BURST_STATUS 0 (PRE_ERR)PRE_ERR 0 (PST_ERR)PST_ERR 0 (ADDR_ERR)ADDR_ERR 0 (CLR_STAT)CLR_STAT

BURST_STATUS=BURST_STATUS_0, TYPE=TYPE_0, AUTO_PRE=AUTO_PRE_0, LEN=LEN_0, AUTO_PST=AUTO_PST_0

Description

Program Burst Control and Status Register

Fields

START

Trigger start of burst program operation
TYPE

Type of memory that burst program is carried out on

0 (TYPE_0): Main Memory

1 (TYPE_1): Information Memory

3 (TYPE_3): Engineering Memory
LEN

Length of burst

0 (LEN_0): No burst operation

1 (LEN_1): 1 word burst of 128 bits, starting with address in the FLCTL_PRGBRST_STARTADDR Register

2 (LEN_2): 2*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR Register

3 (LEN_3): 3*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR Register

4 (LEN_4): 4*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR Register
AUTO_PRE

Auto-Verify operation before the Burst Program

0 (AUTO_PRE_0): No program verify operations carried out

1 (AUTO_PRE_1): Causes an automatic Burst Program Verify after the Burst Program Operation
AUTO_PST

Auto-Verify operation after the Burst Program

0 (AUTO_PST_0): No program verify operations carried out

1 (AUTO_PST_1): Causes an automatic Burst Program Verify before the Burst Program Operation
BURST_STATUS

Status of a Burst Operation

0 (BURST_STATUS_0): Idle (Burst not active)

1 (BURST_STATUS_1): Burst program started but pending

2 (BURST_STATUS_2): Burst active, with 1st 128 bit word being written into Flash

3 (BURST_STATUS_3): Burst active, with 2nd 128 bit word being written into Flash

4 (BURST_STATUS_4): Burst active, with 3rd 128 bit word being written into Flash

5 (BURST_STATUS_5): Burst active, with 4th 128 bit word being written into Flash

7 (BURST_STATUS_7): Burst Complete (status of completed burst remains in this state unless explicitly cleared by SW)
PRE_ERR

Burst Operation encountered preprogram auto-verify errors
PST_ERR

Burst Operation encountered postprogram auto-verify errors
ADDR_ERR

Burst Operation was terminated due to attempted program of reserved memory
CLR_STAT

Clear status bits 21-16 of this register

Links

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Register License

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data